mp38115 ultra low voltage, 4a, 5.5v synchronous step-down switching regulator mp38115 rev. 0.92 www.monolithicpower.com 1 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. the future of analog ic technology description the mp38115 is an internally compensated 1.5mhz fixed frequency pwm synchronous step-down regulator. mp38115 operates from a 1.1v to 5.5v input and generates an output voltage as low as 0.8v. the mp38115 integrates a 60m ? high-side switch and a 60m ? synchronous rectifier for high efficiency without an external schottky diode. with peak current mode control and internal compensation, the mp38115 based solution delivers a very compact footprint with a minimum component count. the mp38115 is available in a small 3mm x 3mm 10-lead qfn package. features ? 4a output current ? input operation range: 1.1v to 5.5v ? 60m ? internal power mosfet switches ? all ceramic capacitor design ? up to 95% efficiency ? 1.5mhz fixed switching frequency ? adjustable output from 0.8v to 0.9xv in ? internal soft-start ? frequency synchronization input ? power good output ? cycle-by-cycle current limiting ? hiccup short circuit protection ? thermal shutdown ? 3mm x 3mm 10-lead qfn package applications ? p/asic/dsp/fpga core and i/o supplies ? printers and lcd tvs ? network and telecom equipment ? point of load regulators ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application mp38115 bs in fb sw en/sync vcc gnd v out 1.1v / 4a v in 1.1v to 5.5v 2.7v to 5.5v v cc off on
mp38115 ? 4a, 5.5v synchronous st ep-down switching regulator mp38115 rev. 0.92 www.monolithicpower.com 2 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. package reference top view fb gnd sw in bs 1 2 3 4 5 en/sync gnd sw in vcc 10 9 8 7 6 exposed pad on backside part number* package MP38115DQ qfn10 (3mm x 3mm) temperature top marking ?40 c to +85 c w2yw * for tape & reel, add suffix ?z (e.g. MP38115DQ?z) for rohs compliant packaging, add suffix ?lf (e.g. MP38115DQ?lf?z) absolute maxi mum ratings (1) in to gnd ................................... ? 0.3v to +6.0v vcc to gnd .............................. ? 0.3v to + 6.0v sw to gnd .......................... ? 0.3v to v in + 0.3v ............................ ? 2.5v to v in + 2.5v for < 50ns fb, en/sync to gnd .................. ? 0.3v to +6.5v bs to sw .................................... ? 0.3v to +6.5v junction temperature...............................150c lead temperature ....................................260c storage temperature .............. ? 65c to +150c recommended operating conditions (2) supply volts v in .............................. 1.1v to 5.5v supply voltage v cc ......................... 2.7v to 5.5v output voltage v out ................. 0.8v to 0.9 x v in operating temperature ............. ? 40c to +85c thermal resistance (3) ja jc qfn10 (3mm x 3mm) ............. 50 ...... 12... c/w notes: 1) exceeding these ratings may damage the device. 2) the device is not guaranteed to function outside of its operating conditions. 3) measured on jesd51-7, 4-layer pcb.. electrical characteristics (4) v cc = v en = 3.6v, t a = +25 c, unless otherwise noted. parameters condition min typ max units supply current v en = v cc v fb = 0.85v 750 a shutdown current v en = 0v, v cc = 5.5v 1 a vcc undervoltage lockout threshold rising edge 2.59 2.69 v vcc undervoltage lockout hysteresis 210 mv regulated fb voltage t a = +25c 0.784 0.800 0.816 v fb input current v fb = 0.85v 50 na en high threshold ?40c t a +85c 1.6 v en low threshold ?40c t a +85c 0.4 v internal soft-start time 120 s high-side switch on-resistance i sw = 300ma 60 m ? low-side switch on-resistance i sw = ?300ma 60 m ? sw leakage current v en = 0v; v cc = 5.5v, v in = 5.5v v sw = 0v or 5.5v ?10 10 a bs under voltage lockout threshold 1.8 v
mp38115 ? 4a, 5.5v synchronous st ep-down switching regulator mp38115 rev. 0.92 www.monolithicpower.com 3 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. electrical characteristics (4) (continued) v in = v en = 3.6v, t a = +25 c, unless otherwise noted. parameters condition min typ max units high-side switch current limit sourcing 6.5 a low-side switch current limit sinking 3.5 a oscillator frequency 1.2 1.5 1.8 mhz maximum synch frequency 2 mhz minimum synch frequency 1 mhz minimum on time 50 ns maximum duty cycle 90 % thermal shutdown threshold hysteresis = 20c 150 c note: 4) production test at +25c. specificat ions over the temperature range are guaranteed by design and characterization. pin functions pin # name description 6 vcc bias supply. this supplies power to both the in ternal control circuit and the gate drivers. a decoupling capacitor to ground is required close to this pin. 4, 7 in input supply. a decoupling capacitor to ground is required close to these pins to reduce switching spikes. 3, 8 sw switch node connection to the inductor. these pins connect to the internal high and low- side power mosfet switches. all sw pins must be connected together externally. 2, 9 gnd ground. connect these pins with larger copper areas to the negative terminals of the input and output capacitors. 5 bs bootstrap. a capacitor between this pin and sw provides a floating supply for the high-side gate driver. 1 fb feedback. this is the input to the error amplifie r. an external resistive divider connects this pin between the output and gnd. the voltage on t he fb pin compares to the internal 0.8v reference to set the regulation voltage. 10 en/sync enable and frequency synchronization input pin. forcing this pin below 0.4v shuts down the part. forcing this pin above 1.6v turns on the part. applying a 1mhz to 2mhz clock signal to this pin synchronizes the internal oscillator frequency to the external clock.
mp38115 ? 4a, 5.5v synchronous st ep-down switching regulator mp38115 rev. 0.92 www.monolithicpower.com 4 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. functional block diagram -- + + -- + logic slope compensation and peak current limit pwm current comparator en comp slope clk en exclk osc en/sync logic soft -start 0.8v 0.5pf 1.2 meg 17pf in vcc uvlo in bs sw sw gnd gnd fb en/sync figure 1?functional block diagram (mp38115)
mp38115 ? 4a, 5.5v synchronous st ep-down switching regulator mp38115 rev. 0.92 www.monolithicpower.com 5 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. functional description pwm control the mp38115 is a cons tant frequency peak- current-mode control pwm switching regulator. refer to the functional block diagram. the high side n-channel dmos power switch turns on at the beginning of each clock cycle. the current in the inductor increases until the pwm current comparator trips to turn off the high side dmos switch. the peak inductor current at which the current comparator shuts off the high side power switch is controlled by the comp voltage at the output of feedback error amplifier. the transconductance from t he comp voltage to the output current is set at 11.25a/v. this current-mode control greatly simplifies the feedback compensation desi gn by approximating the switching converter as a single-pole system. only type ii compensation network is needed, which is integrated into the mp38115. the loop bandwidth is adjusted by changing the upper resistor value of the resist or divider at the fb pin. the internal compensation in the mp38115 simplifies the compensation design, minimizes external component counts, and keeps the flexibility of external compensation for optimal stability and transient response. enable and frequency synchronization (en/sync pin) this is a dual function input pin. forcing this pin below 0.4v for longer than 4us shuts down the part; forcing this pin above 1.6v for longer than 4s turns on the part. applying a 1mhz to 2mhz clock signal to this pin also synchroni zes the internal oscillator frequency to the external clock. when the external clock is used, the part tu rns on after detecting the first few clocks regardless of duty cycles. if any on or off period of the clock is longer than 4s, the signal will be intercepted as an enable input and disables the synchronization. soft-start and output pre-bias startup when the soft-start period st arts, an internal current source begins charging an internal soft-start capacitor. during soft-start, the voltage on the soft- start capacitor is connec ted to the non-inverting input of the error amplifier. the soft-start period lasts until the voltage on t he soft-start capacitor exceeds the reference voltage of 0.8v. at this point the reference voltage takes over at the non- inverting error amplifier input. the soft-start time is internally set at 120s. if the output of the mp38115 is pre-biased to a certain voltage during startup, the ic will disable the switching of both high-side and low-side switches until t he voltage on the internal soft-start capacitor ex ceeds the sensed output voltage at the fb pin. over current protection the mp38115 offers cycle-to-cycle current limiting for both high-side and low- side switches. the high- side current limit is relative ly constant regardless of duty cycles. when the output is shorted to ground, causing the output voltage to drop below 70% of its nominal output, the ic is shut down momentarily and begins discharging the so ft start capacitor. it will restart with a full soft- start when the soft- start capacitor is fully discharged. this hiccup process is repeated until the fault is removed. bootstrap (bst pin) the gate driver for the high-side n-channel dmos power switch is supplied by a bootstrap capacitor connected between the bs and sw pins. when the low-side switch is on, t he capacitor is charged through an internal boost diode. when the high-side switch is off and the low-side switch turns on, the voltage on the bootstrap c apacitor is boosted above the input voltage and the in ternal bootstrap diode prevents the capacitor from discharging.
mp38115 ? 4a, 5.5v synchronous st ep-down switching regulator mp38115 rev. 0.92 www.monolithicpower.com 6 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. application information output voltage setting the external resistor divider sets the output voltage (see page 1, schematic diagram). the feedback resistor r1 also sets the feedback loop bandwidth with the internal compensation (refer to description function). the relation between r1 and feedback loop bandwidth (f c ), output capacitance (c o ) is as follows: ) f ( c ) khz ( fc 10 24 . 1 ) k ( 1 r o 6 = the feedback loop bandwidth (f c ) is no higher than 1/10 th of switching frequency of mp2107. in the case of ceramic capacitor as c o , it is usually set in the range of 50khz and 150khz for optimal transient performance and good phase margin. if an electrolytic capacitor is used, the loop bandwidth is no higher than 1/4 of the esr zero frequency (f esr ). f esr is given by: esr esr o 1 f 2r c = for example, choose f c =70khz with a ceramic capacitor, c o =47 f, r1 is estimated to be 400k ? . r2 is then given by: out r1 r2 = v -1 0.8v table 1?resistor selection vs. output voltage setting vout r1 r2 l cout (ceramic) 1.2v 400k ? 806k ? 0.47 h-1 h 47 f 1.5v 400k ? 453k ? 0.47 h-1 h 47 f 1.8v 400k ? 316k ? 0.47 h-1 h 47 f 2.5v 400k ? 187k ? 0.47 h-1 h 47 f 3.3v 400k ? 127k ? 0.47 h-1 h 47 f inductor selection a 0.47h to 1h inductor with dc current rating at least 25% higher than the maximum load current is recommended for most applications. for best efficiency, the inductor dc resistance shall be <10m ? . see table 2 for recommended inductors and manufacturers. for most designs, the inductance value can be derived from the following equation: out in out in l osc vx(v-v) l= vx ixf where ? i l is inductor ripple current. choose inductor ripple current approximately 30% of the maximum load current, 4a. the maximum inductor peak current is: l l(max) load input capacitor selection the input capacitor reduces the surge current drawn from the input and the switching noise from the device. the input capacitor impedance at the switching frequency shall be less than input source impedance to prevent high frequency switching current passing to the input source. ceramic capacitors with x5r or x7r dielectrics are highly recommended because of their low esr and small temperature coefficients. for most applications, a 47f capacitor is sufficient. output capacitor selection the output capacitor keeps output voltage ripple small and ensures a stable regulation loop. the output capacitor impedance shall be low at the switching frequency. ceramic capacitors with x5r or x7r dielectrics are recommended. the output ripple ? v out is approximately: ? out in out out in osc osc 3 vx(v-v) 1 v x(esr + ) v xf xl 8xf xc external schottky diode for this part, an external schottky diode is recommended to be placed close to "sw" and "gnd" pins, especially when the output current is larger than 2a. with the external schottky diode, the voltage spike and negative kick on "sw" pin can be minimized; moreover, the conversion efficiency can also be improved a little. for the external schottky diode selection, it's noteworthy that the maximum reverse voltage rating of the external diode should be larger than the maximum input voltage. as for the current rating of this diode, 0.5a rating should be sufficient.
mp38115 ? 4a, 5.5v synchronous st ep-down switching regulator mp38115 rev. 0.92 www.monolithicpower.com 7 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. table 2?suggested surface mount inductors manufacturer part number inductance ( h) max dcr (m ? ) current rating (a) dimensions l x w x h (mm 3 ) wurth electronics 744310055 0.55 4.5 14 76.93 744310095 0.95 7.4 11 76.93 toko b1015as-1r0n 1 11 6.9 8.48.34 pcb layout guide pcb layout is very important to achieve stable operation. it is highly recommended to duplicate evb layout for optimum performance. if change is necessary, please follow these guidelines as follows. here, the typical application circuit is taken as an example to illustrate the key layout rules should be followed. 1) for mp38115, a pcb layout with more than (or) four layers is recommended. 2) the high current paths (gnd, in and sw) should be placed very close to the device with short, direct and wide traces. 3) for mp38115, two input ceramic capacitors (2 x (10 f~22 f)) are strongly recommended to be placed on both sides of the mp38115 package and keep them as close as possible to the ?in? and ?gnd? pins. 4) an rc low pass filter is recommended for vcc supply. the vcc decoupling capacitor must be placed as close as possible to ?vcc? pin and ?gnd? pin. 5) the external feedback resistors shall be placed next to the fb pin. keep the fb trace as short as possible. don?t place test points on fb trace if possible. 6) keep the switching node sw short and away from the feedback network. top layer
mp38115 ? 4a, 5.5v synchronous st ep-down switching regulator mp38115 rev. 0.92 www.monolithicpower.com 8 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. inner layer1 inner layer2 bottom layer figure2?recommended pcb layout of mp38115
mp38115 ? 4a, 5.5v synchronous st ep-down switching regulator mp38115 rev. 0.92 www.monolithicpower.com 9 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. typical application circuits bs in vcc sw en/sync fb gnd mp38115 4,7 5 3, 8 1 2,9 6 10 vin 2.7v to 5.5v vout 1. 8v/ 4a c3 47uf r1 400k r2 316k l1 1uh c4 100nf c2 22uf r3 100k r4 10 c4 1uf d1 b0530 c1 22uf figure3?typical application circuit of mp38115
mp38115 ? 4a, 5.5v synchronous st ep-down switching regulator notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp38115 rev. 0.92 www.monolithicpower.com 10 8/11/2009 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2009 mps. all rights reserved. package information qfn10 (3mm x 3mm) side view top view 1 10 6 5 bottom view 2.90 3.10 1.45 1.75 2.90 3.10 2.25 2.55 0.50 bsc 0.18 0.30 0.80 1.00 0.00 0.05 0.20 ref pin 1 id marking 1.70 0.50 0.25 recommended land pattern 2.90 note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeter max. 4) drawing conforms to jedec mo-229, variation veed-5. 5) drawing is not to scale. pin 1 id see detail a 2.50 0.70 pin 1 id option b r0.20 typ. pin 1 id option a r0.20 typ. detail a 0.30 0.50 pin 1 id index area
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